1. Field of the Invention
The present invention relates to a semiconductor chip with projecting electrodes, which contains semiconductor devices composed of electric circuits including circuit elements, such as transistors or resistors, on a semiconductor wafer and connecting the circuit elements to each other via wirings, and a method of inspecting the semiconductor chip with projecting electrodes.
2. Description of the Prior Art
FIG. 12 is a plan view showing a semiconductor wafer on which a number of semiconductor chips with projecting electrodes (hereinafter, referred to as xe2x80x9cbumpsxe2x80x9d) are formed in such a manner as to be laid out as shown in the figure. In the figure, reference numeral 1 denotes a semiconductor wafer; 2 is a bump formation region; 31 is a semiconductor chip with 100% bumps, in which the bumps are perfectly formed on external connection pads; 41 is a semiconductor chip with 90% bumps, in which about 10% of the bumps are lacking; and 51 is a semiconductor chip with 70% bumps, in which about 30% of the bumps are lacking.
These semiconductor chips 31, 41 and 51 with bumps are fabricated by a process of forming circuit elements such as transistors on a semiconductor wafer by use of techniques such as chemical vapor deposition (CVD) and ion implantation; stacking, on the wafer, wirings for connecting the circuit elements to each other to form semiconductor devices; and forming, by use of a mask set in a bump formation region, a bump underlying metal layer, and projecting electrodes or bumps 6 made from gold or solder on external connection pads through processes of sputtering, electrolytic plating, or the like.
FIGS. 13 to 15 are plan views each showing a prior art configuration example of a semiconductor chip with bumps, wherein FIG. 13 shows a semiconductor chip with 100% bumps; FIG. 14 shows a semiconductor chip with 90% bumps; and FIG. shows a semiconductor chip with 70% bumps. In these figures, like characters denote like components or corresponding parts, and the explanation thereof is omitted. Reference numeral 6 denotes a bump; 8 is an external connection pad with a bump; 11 is a boundary of the bump formation region 2 depicted on a large scale; and 12 is a bump non-formation pad.
Next, the operation will be described below.
Each of the semiconductor chips 31, 41 and 51 with bumps includes internal circuits A to D containing input/output buffers, logic circuits, and the like which are electrically connected to the external connection pads 8 for signal exchange via the external connection pads 8.
The prior art semiconductor chip with bumps and the inspecting method thereof, configured as described above, have problems. That is to say, upon bump formation, there may occur lacking bumps 6 at the boundary of the bump formation area, that is, at the bump formation region boundary 11 or at least one of four corners of each of the semiconductor chips 41 and 51 with bumps positioned at the periphery of a wafer, to form the bump non-formation pads 12 thereat, thereby reducing the reliability of integrated circuits (ICs) constituting semiconductor devices.
Conventionally, a semiconductor chip with bumps partially lacking upon bump formation has been selected in a wafer test by a manner of forming, on a semiconductor chip, positioned out of the bump formation region 2, a short-circuit bump unit 24 in which the bumps 6 are short-circuited to each other, and detecting the short-circuit bump unit 24 by an IF test performed at the beginning of a wafer test.
FIGS. 16 to 18 are plan views each showing a prior art semiconductor chip with short-circuit bump units, wherein FIG. 16 shows a semiconductor chip 31xe2x80x2 with 100% short-circuit bump units; FIG. 17 shows a semiconductor chip 41xe2x80x2 with 90% short-circuit bump units; and FIG. 18 shows a semiconductor chip 51xe2x80x2 with 70% short-circuit bump unit. In these figures, like characters denote like components or corresponding parts, and the explanation thereof is omitted. Reference numeral 24 denotes a short-circuit bump unit, and character X is a region in which the short-circuit bump unit 24 is formed.
Even if the above short-circuit bump units are formed, however, there arises another problem. That is to say, as shown in FIGS. 15 to 18, for each of the semiconductor chips 41, 41xe2x80x2 and 51, 51xe2x80x2 positioned at the boundary of the bump formation region 2 the semiconductor wafer 1, there is occurs lacking of the short-circuit bump unit itself due to lacking of the bumps 6, with a result that it fails to reject a chip with bumps 6, part of which are lacking, in the wafer test.
Since the semiconductor chip at the boundary of the bump-formation region 2 cannot be selected by the wafer test, the bump formation state of the chip must be manually determined after the wafer test, and if the chip is determined as a defective one, a defective mark must be manually recorded on the chip. In particular, when a large number of semiconductor chips are laid out on one semiconductor wafer, there occur problems such that it takes a lot of time for selection by visual inspection; the visual inspection cost becomes high; a defective chip is mixed into the subsequent step due to an oversight by manual inspection; and the reliability of ICs is reduced. The manual work may cause another problem in erroneous formation of a short-circuit bump unit on a semiconductor chip outside of the bump formation region 2. In such a case, the semiconductor chip, even if it has no problem in terms of electrical characteristic of ICs, is determined as a defective chip by the wafer test because of the presence of the short-circuit bump unit. This gives rise to an inconvenience that a non-defective chip is erroneously wasted.
The prior art semiconductor chip 41xe2x80x2 with about 10% bumps lacking, which bumps are formed with short-circuit bump units, can be selected as a defective one by the IF test because the external connection pads 8 are short-circuited via the bumps 6.
On the contrary, although the prior art semiconductor chip 51xe2x80x2 with bumps in which about 30% of the bumps based on the total area of the chip are lacking must be generally selected as a defective one for ensuring the reliability of the completed semiconductor device, it cannot be selected as a defective one. The reason for this is that since the short-circuit bump unit 24 is not formed in the region X, there is no problem in terms of contact of a probe in the wafer test irrespective of no formation of the bumps 6 on the external connection pads 8 because of the presence of the underlying pads, so that a desired result is erroneously obtained in the above IF test.
As a result, in the actual fabrication process, to select these defective products, the semiconductor chips 31, 41, 51 and 31xe2x80x2, 41xe2x80x2 and 51xe2x80x2 having bumps are required to be visually inspected. Such a manual inspection, however, causes a variation in inspected results, and accordingly a chip, which should be selected as a defective one for maintaining the reliability of ICs, remains as a non-defective one, giving rise to a problem that there is a possibility of formation of a semiconductor device using such a defective chip in terms of lacking bumps.
In the above IF test, depending on the order of inspecting the portions at which bumps are lacking and the external connection pads 8, there is a possibility that the chip is determined as a defective one after inspection of a plurality of the good external connection pads 8 with bumps. In such a case, there arises a problem that the time required for inspecting the plurality of the good external connection pads 8 until the determination is wasted.
A schematic view showing a configuration of a short-circuit bump unit of the region X in FIG. 16, in which the perspective view of the short-circuit bump is shown in FIG. 19(a) and a sectional view taken on line 19bxe2x80x9419b is shown FIG. 19(b). In these figures, like characters denote like components and corresponding parts, and the explanation thereof is omitted. Reference numeral 14 denotes a bump underlying metal as a buffer layer between the bump 6 and the external connection pad 8 laid under the bump 6; 15 is a protective film for preventing moisture absorption or the like stacked on the uppermost layer of the chip; and 18 is a probe used for the wafer test. The contact state of the probe is schematically shown in FIG. 19(a).
With this configuration, the shape of the bump 6 is affected by a step of the underlying structure due to a difference in height between the external connection pad 8 and the protective film 15, and has a step which is shown in FIG. 19(a). This causes a problem that there occur a variation in height of the bumps upon mounting of the semiconductor chip with bumps and a variation in contact pressure of the probe in the wafer test.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor chip with projecting electrodes or bumps, which is configured such that if bumps of the chip are partially lacking, such a chip can be easily determined as a defective one and that the surfaces of the bumps are flattened, and a method of inspecting the semiconductor chip with bumps.
To achieve the above object, according to an aspect of the present invention, there is provided a method of inspecting a semiconductor chip with projecting electrodes, including the steps of: measuring an electric characteristic of each of electrode terminals for detecting formation of projecting electrodes arranged along four corners of the peripheral edge of the semiconductor chip; and determining the semiconductor chip as a defective one in terms of formation of projecting electrodes if the measured result does not conform to a desired characteristic.
With this configuration, a chip with projecting electrodes or bumps part of which are lacked, occurring at the boundary of a bump formation region, can be automatically determined as a defective one by a wafer test without adoption of visual inspection. Thus, there can be obtained an effect of reducing a time required for-visual inspection of semiconductor chips with projecting electrodes after the wafer test, thereby reducing the fabrication cost of the semiconductor chips with projecting electrodes.
According to an aspect of the present invention, there is provided a semiconductor chip with projecting electrodes, wherein an electrode terminal is prepared by opening a protective film as an underlying film for a projecting electrode together with upper portions of external connection pads under the projecting electrode and a region in which the electrode terminal is to be formed, and forming the electrode terminal in the opening portion, whereby the surface of the electrode terminal is flattened.
With this configuration, since such a step as to follow the irregularity of the protective film is not formed on the surface of the projecting electrode, there can be obtained an effect of equalizing the contact pressure of a probe when the probe is brought in contact with the surface of the projecting electrode upon the wafer test.
According to an aspect of the present invention, there is provided a semiconductor chip with projecting electrodes including: electrode terminals for detecting formation of projecting electrodes arranged at least two positions; and a projecting electrode detecting wiring arranged in such a manner as to be electrically connected to the electrode terminals and to extend, over the entire peripheral edge of the semiconductor chip, between the peripheral edge and positions at which external connection pads are formed.
With this configuration, non-defective/defective of the semiconductor chip with projecting electrodes can be automatically determined by the wafer test by connecting a probe to the electrode terminals for detecting formation of the projecting electrodes or projecting electrode detecting pads connected to the projecting electrode detecting wiring, and by comparing the result of measuring the electric characteristic with a desired characteristic. Accordingly, like the above effects, there can be obtained effects of shortening an inspecting time, and improving the reliability, for example, by preventing human error and mixing of a defective chip into the subsequent step.
According to an aspect of the present invention, there is provided a method of inspecting a semiconductor chip with projecting electrodes, including the steps of: measuring an electric characteristic of an electrode terminal for detecting formation of projecting electrodes and determining the semiconductor chip as a defective one if the measured result does not conform to a desired characteristic.
With this configuration, the chip with projecting electrodes part of which are lacked can be detected and determined as a defective one by the wafer test, and accordingly, like the above effects, there can be obtained an effect of reducing a time required for visual inspection of semiconductor chips with projecting electrodes after the wafer test, thereby reducing the fabrication cost of the semiconductor chips with projecting electrodes.
According to an aspect of the present invention, there is provided a method of inspecting a semiconductor chip with projecting electrodes, wherein an electrode terminal for detecting formation of projecting electrodes has a structure in which two external connection pads are to be short-circuited by formation of a projecting electrode, and if the connection between the two external connection pads cannot be perfectly short-circuited, the electric characteristic does not conform to a desired characteristic, and thus, the semiconductor chip is determined as a defective one in terms of formation of projecting electrodes.
With this configuration, there can be obtained an effect of automatically selecting chips with projecting electrodes part of which are lacked by the IF test performed at the beginning of the wafer test, thereby reducing the fabrication cost of the semiconductor chips with projecting electrodes.
According to an aspect of the present invention, there is provided a semiconductor chip with projecting electrodes, including a projecting electrode detecting wiring for electrically connecting an external connection pad arranged along the peripheral edge to an internal circuit via an electrode terminal for detecting formation of projecting electrodes.
With this configuration, since the chip with bumps part of which are lacked can be selected by comparison of an electric characteristic such as a diode characteristic with a desired characteristic in addition to the above-described IF test, there can be obtained an effect of improving the reliability of the inspection in addition to the above-described effects.
According to an aspect of the present invention, there is provided a method of inspecting a semiconductor chip with projecting electrodes, including the steps of measuring an electric characteristic across an electrode terminal for detecting formation of projecting electrodes via external connection pads, and determining the semiconductor chip as a defective one in terms of formation of projecting electrodes if the measured result does not conform to a desired characteristic.
With this configuration, the above IF test, a function test, and inspection of an electric characteristic such as a diode characteristic can be performed by making use of the projecting electrode detecting wiring. As a result, like the above effects, there can be obtained effects of shortening the inspecting time, preventing human error and mixing of a defective chip into the subsequent step, and improving the reliability of the inspection.
According to an aspect of the present invention, there is provided a method of inspecting a semiconductor chip with projecting electrodes, wherein an electrode terminal for detecting formation of projecting electrodes has a structure in which two external connection pads are short-circuited by formation of a projecting electrode; and it is measured whether the connection between the two external connection pads is opened or short-circuited and also a diode characteristic is measured, and if these electric characteristics do not conform to respective desired characteristics, the semiconductor chip is determined as a defective one in terms of formation of projecting electrodes.
With this configuration, a defective chip in terms of formation of projecting electrodes can be automatically selected in the wafer test by inspection of the diode characteristic in addition to the IF test, and accordingly, like the above effects, there can be obtained effects of shortening an inspecting time and improving the reliability of the inspection.